1. Field of the Invention
This invention relates to dynamic random access memory (DRAM) and more particularly to DRAM circuits and fabrication processes that will enhance performance.
2. Description of Related Art
All circuits in a DRAM chip, such as the memory cell, sense amplifier, row and column decoders, and input/output buffers, are presently designed and fabricated using the same gate oxide thickness. This design and fabrication approach has nearly satisfied all applications in personal computers. The speed and performance of DRAM have not been a determining factor for performance of personal computers at clocking speed less than 133 MHz. As the deep sub-micrometer process (0.18 .mu.m-0.13 .mu.m feature size) is becoming more prevalent for fabricating integrated circuits such as DRAM, the operating voltage needs to be reduced. The reduction in operating voltage will degrade the speed of the DRAM circuits. At this same time, the clocking frequency is increasing beyond 133 MHz and the access time and cycle time of the DRAM chip within a personal computer memory is having a larger impact on performance.
Historically, the thickness of the gate oxide used in the fabrication of the metal oxide semiconductor (MOS) transistors has been adjusted to insure the reliability of the pass transistor within the memory cell. To insure proper operation, the word line voltage is boosted by a voltage at least one threshold voltage V.sub.T greater than the supply voltage of the memory cell array. This voltage will cause a higher voltage field within the gate oxide of the pass transistor, thus requiring the increased thickness. This increased thickness of the gate oxide is presently used throughout all the MOS transistors of all the circuits of the DRAM chip. The peripheral circuits external to the memory cell array will have an operational voltage less than the voltage created for the word line and thus will have degraded performance because of the thicker gate oxide. This degraded performance of the peripheral circuits will limit the improvement of the access and cycle time necessary to meet the performance requirements of the future personal computer applications.
The concept of an integrated circuit chip having multiple thickness of gate oxide used in the fabrication of MOS transistors within an integrated circuit is discussed in "Embedded DRAM Technologies," H. Ishiuchi et al., page 33, IEDM Technical Digest, 1997. Ishiuchi et al. describes the use of an embedded DRAM circuit incorporated with an array of logic circuits. The embedded DRAM will have MOS transistors with a thicker gate oxide while the separate logic circuits will have MOS transistors with a thinner gate oxide. The performance of the embedded DRAM will have the same performance issues as described above, since the peripheral circuits of the embedded DRAM will have the thicker gate oxide.
U.S. Pat. No. 5,057,449 (Lowery et al.), U.S. Pat. No. 5,293,336 (Ishii et al.), U.S. Pat. No. 5,576,226 (Hwang et al.), U.S. Pat. No. 5,083,172 (Kiyono), and U.S. Pat. No. 4,525,811 (Masuoka) each discloses DRAM devices and methods of fabrication where a thin gate oxide is used in the fabrication of the MOS transistors of the peripheral circuitry of a DRAM, while a thick gate oxide is used in the fabrication of the MOS pass transistor within the memory cells of the DRAM. The use of the thin gate oxide in the fabrication of the MOS transistors in the peripheral circuitry will improve performance of the DRAM device, but the MOS transistors within the boost voltage circuit, the word line driver, and the data input/output drivers have voltages that are larger than the power supply voltage source. This will increase the electrical field present within the gate oxide of the MOS transistors and increase the reliability problem. The reliability problem is the increase of the probability of failure of the gate oxide due to the stress of the electrical field degrading the gate oxide. This will reduce the overall reliability of the DRAM chip.
U.S. Pat. No. 5,426,065 (Chan et al.), U.S. Pat. No. 5,327,002 (Motoyoshi), and U.S. Pat. No. 5,703,392 (Guo) each describes Static Random Access Memory (SRAM) that has different gate oxide thickness used within each memory cell to modify the MOS threshold voltages as necessary to improve operation.
U.S. Pat. No. 5,251,172 (Yamauchi) describes a DRAM wherein the sense amplifier voltage is adjusted by having different power supply voltage sources V.sub.cc and different substrate biasing voltage sources -V.sub.bb connected to the transistors of the sense amplifier. Adjusting the threshold voltage V.sub.T of each of the MOS transistors within the sense amplifier will decrease the delay present before sense amplification begins.
U.S. Pat. No. 5,595,922 (Tigelaar et al.), U.S. Pat. No. 5,502,009 (Lin), U.S. Pat. No. 5,672,521 (Barsan et al.), and U.S. Pat. No. 5,497,021 (Tada) each discloses methods for forming gate oxides of MOS transistors of different thickness upon a semiconductor substrate.